(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to the formation of shallow trench isolation structures with improved isolation fill and surface planarity.
(2) Description of the Prior Art
As integrated circuit feature sizes continue to shrink, one of the limiting factors in this size reduction is the technique for active area isolation. Traditionally in the art, active areas have been isolated from each other through the formation of local oxidation of silicon, or LOCOS, structures. LOCOS structures provide good electrical isolation of active areas such as transistor source and drain regions. However, LOCOS structures consume substantial amounts of silicon surface area. This means that the available area for active devices such as transistors is reduced. Further, the LOCOS structure is three-dimensional and creates a non-planar surface topology that adversely affects the process yield and complexity of the processing steps that come after the LOCOS formation.
To reduce the silicon area used for isolation regions and to improve the planarity of these regions, a new technique, called shallow trench isolation, or STI, has been developed. In STI, trenches or grooves are etched into the top surface of the silicon wafer. These grooves are then filled with an isolating dielectric such as silicon oxide. This isolating dielectric is then made planar to the surface of the substrate by etching or chemical mechanical polishing (CMP). STI structures made in this way can be made substantially smaller than comparable LOCOS structures. Therefore less of the silicon surface is used for isolation and more is available for active devices. Since the STI structures are made planar, the processing problems presented by the LOCOS surface topology are solved.
Even with its advantages when compared to LOCOS, prior art STI structures do have several problems associated with the integrity and planarity of the isolating dielectric.
The first problem is that, under certain conditions, voids can form in the isolating dielectric that fills the trench. A cross-sectional view of a partially completed STI structure is shown in FIG. 1. A semiconductor substrate 11 is shown. Layers of pad oxide 12 and silicon nitride 13 have been deposited on the surface of the substrate 11. A trench has been etched through the silicon nitride 13 and pad oxide 12 and partially into the substrate 11. An isolation dielectric 14 such as silicon oxide is deposited over the silicon wafer to fill the STI trench.
As can be seen in the illustration, a void has formed in the isolation dielectric 14. The likelihood of this void forming increases as the aspect ratio of the trench increases. The aspect ratio is the ratio between the depth of the trench L1 and the width of the trench L2. It is observed in the art that if the aspect ratio (L1:L2) is greater than 1:1, then voids will form in the isolation dielectric 14. Unfortunately, aspect ratios exceeding 1:1 and even approaching 1.5:1 are needed as integrated circuit device geometry continues to decrease. Further, if such a void forms, then, when the surface conductive layers are later deposited, residue from these conductive materials can be trapped in this void. These trapped conductive residues can then cause electrical short paths between layer elements that were supposed to be electrically isolated.
The second problem is that the edges of the top surface of the isolation dielectric of the STI are typically recessed at the corners of substrate active area. FIG. 2 illustrates this problem. After the STI trench is formed in the substrate 21 and filled with the isolation dielectric 22, the wafer is subjected to chemical mechanical polishing, or CMP, cleaning, and etching processes to remove excess oxide and nitride material. In STI structures typical in the art, the anisotropic component of the oxide-etching step will cause the recession of the isolation dielectric surface 23 near the edges of the STI trench. Unfortunately, such edge recession exposes the corners of the silicon substrate 21 in the active area. This causes sub-threshold leakage currents and reduction in gate oxide dielectric breakdown for the active device formed in this area adjacent to the STI.
The third problem is that the top corners 24 of the STI trench are relatively sharp, as seen in FIG. 2. This topology causes the STI structure to be susceptible to parasitic corner transistor formation.
Several prior art approaches attempt to reduce the likelihood or severity of isolation dielectric voids, exposure of the substrate active area due to edge recession, and to improve the roundness of the top corners of the STI structure. U.S. Pat. No. 5,747,866 to Ho et al shows a process which can round the corners of the STI interface with the active area through the formation of an oxide liner. U.S. Pat. No. 5,719,085 to Moon et al teaches the STI process that undercuts the pad oxide layer with an HF etch and forms an oxide liner that rounds the active area corner. U.S. Pat. No. 4,839,306 to Wakamatsu shows an isolation method that uses etching to make the active area corners rounded.